A power device is a semiconductor element in which a large current flows, and is expected to have a high breakdown voltage and a low loss. Conventionally, power devices in which silicon (Si) semiconductor is used have been in the main stream. In recent years, however, power devices in which silicon carbide (SiC) semiconductor is used are drawing attention and are under development. A silicon carbide semiconductor has a breakdown field which is one digit higher than that of silicon, and therefore is able to maintain a reverse voltage even if the depletion layer of a PN junction or a Schottky junction is reduced in thickness. Since this makes possible a thin device thickness and a high doping concentration, silicon carbide is expected as a power device material with a low ON resistance, a high breakdown voltage, and a low loss.
FIG. 10 is a cross-sectional view showing the structure of a double implantation MOSFET, as an example of a silicon carbide semiconductor device. On a substrate 101 which is made of a silicon carbide having a low resistance, a high-resistance layer 102 having a higher resistance than that of the substrate 101 is epitaxially grown. In the surface region of the high-resistance layer 102, a p type well region 103 is formed via selective ion implantation, inside which an high-concentration n type source region 105 and a p type p+ contact region 104 located in a region surrounded by the source region 105 are provided via ion implantation.
From above the high-resistance layer 102 interposed between the two well regions 103 to above the end portions of the source regions 105 within the two well regions 103, a gate insulating film 106 which is made of a thermal oxide film is formed. A gate electrode 109 is formed on the gate insulating film 106. From above the p+ contact region 104 to above the end portions of the source region 105 located on both ends thereof, a source electrode 108 which is in ohmic contact with the contact region 104 is provided. Furthermore, over the entire rear face of the substrate 101, a drain electrode 107 which is in ohmic contact with the substrate 101 is provided.
An interlayer insulating film 110 is deposited on the high-resistance layer 102, the p type well regions 103, the p+ contact regions 104, and the source regions 105. In the interlayer insulating film 110, contact holes which respectively reach the source electrodes 108 and the gate electrodes 109 are provided. On the interlayer insulating film 110, upper wiring 111 which is made of a thickness 2 μm of aluminum and which fills in the contact holes is provided. The above structure is disclosed in Patent Document 1, for example.
In order to reduce the contact resistance of the drain electrode 107, it is preferable to perform an ion implantation for the rear face of the substrate 101, thus forming an ion implantation layer having a high concentration of impurity on the rear face of the substrate 101 (Patent Document 2).
In the case of silicon carbide semiconductor, it is difficult to effect thermal diffusion of impurities, and therefore an ion implantation must be performed in order to form the diffusion layers such as the source regions 105, the well regions 103, and the contact regions 104. In the case of a silicon semiconductor element, formation of diffusion layers via thermal diffusion is possible, but miniaturization in the recent years has made it important to form diffusion layers via ion implantation.
However, an ion implantation for silicon carbide semiconductor has a unique problem in that the ion implantation needs to be performed at a high temperature. Silicon carbide has a high cohesive strength, and a high temperature of 1600° C. or more is needed for an activation annealing to be performed after the ion implantation. However, such an activation annealing alone will not suffice, and it is considered necessary to maintain the silicon carbide substrate at a high temperature of 400° C. or more even while the ion implantation is being performed (e.g., Patent Document 4, Non-Patent Document 1, Non-Patent Document 2). The reason is that performing an ion implantation at a high temperature makes it possible to reduce the surface roughening after the activation annealing and reduce an increase in the sheet resistance of the diffusion layers, thus enhancing the activation rate of impurities.
Conventionally, a high-temperature ion implantation is performed while supporting a silicon carbide substrate (semiconductor wafer) on a carbon susceptor having a resistance heater embedded therein, for example. A mechanical device for fixing a semiconductor wafer via screwing is attached to the carbon susceptor, and, each time upon ion implantation, an operator needs to fix the semiconductor wafer onto the carbon susceptor via screwing. Therefore, the semiconductor wafer cannot be automatically conveyed, and the vacuum in the ion implantation chamber is broken for allowing the semiconductor wafer to be fixed onto the carbon susceptor. Moreover, after fixing the semiconductor wafer onto the carbon susceptor, a vacuum evacuation and a temperature elevation in the ion implantation chamber need to be performed, and then the ion implantation must be performed. The temperature elevation is performed, in the interior of the ion implantation apparatus, by heating the semiconductor wafer fixed to the carbon susceptor with the aforementioned resistance heater internalized in the carbon susceptor, or with an externally-provided lamp annealer, and so on. After the high-temperature ion implantation is completed, the temperature of the semiconductor wafer and the carbon susceptor is lowered, and after again breaking the vacuum in the ion implantation chamber, the semiconductor wafer having experienced the implantation is taken out to the exterior. Thus, the conventional method which fixes a semiconductor wafer onto a carbon susceptor via screwing has a problem of very low throughput and poor mass producibility.
In order to solve the aforementioned problems of a high-temperature ion implantation step, ion implantation apparatuses employing a high-temperature electrostatic chuck are being studied in the recent years. Generally speaking, an electrostatic chuck is a device for fixing a wafer by using an electrostatic force, and is disclosed in Patent Document 3, for example. Hereinafter, the construction of an electrostatic chuck will be described with reference to FIG. 11. FIG. 11 is a cross-sectional view showing the schematic structure of an electrostatic chuck.
The illustrated electrostatic chuck 6 includes a base 21 which is made of an insulator, a first electrode 23a and a second electrode 23b which are embedded within the base 21, and a surface dielectric layer 22 which is deposited on the surface of the base 21. The first electrode 23a and the second electrode 23b are connected to a power supply 24 which is external to the electrostatic chuck 6. When voltages of opposite polarities are applied to the first electrode 23a and the second electrode 23b with the power supply 24, an electric charge is induced on the surface of the surface dielectric layer 22. When an attracted object such as a semiconductor wafer 1 is placed so as to closely face the surface dielectric layer 22, an electric charge of the opposite polarity from the electric charge which is induced on the surface of the surface dielectric layer 22 is induced on the opposing face of the semiconductor wafer 1, so that a Coulomb force or a Johnsen-Rahbek force acts therebetween, thus making it possible to fix the attracted object onto the electrostatic chuck 6 via attraction (chucking).
In the present specification, a region of the surface of an electrostatic chuck that comes in contact with an attracted object will be referred to as an “attracting face”. This attracting face may also be referred to as a chuck face or a contact face. On the other hand, a surface of a semiconductor wafer that comes in contact with the “attracting face” of an electrostatic chuck will be referred to as an “attracted face”.
In order to heat a semiconductor wafer at the time of ion implantation, a heating mechanism such as a heater (not shown) is provided on the aforementioned electrostatic chuck, and the electrostatic chuck is constantly heated to a high temperature (e.g. 400° C.) even before the semiconductor wafer is attracted. By thus attracting the semiconductor wafer with the electrostatic chuck which is heated to a high temperature, the semiconductor wafer can be heated via heat conduction, whereby a high-temperature ion implantation can be realized.                [Patent Document 1] Japanese Laid-Open Patent Publication No. 2004-304174        [Patent Document 2] Japanese Laid-Open Patent Publication No. 2003-86816        [Patent Document 3] Japanese Laid-Open Patent Publication No. 2003-249544        [Patent Document 4] Japanese Laid-Open Patent Publication No. 2006-324585        [Non-Patent Document 1] Seiji Imai et al., Material Science Forum, Vol. 5, 338-342 (2000) pp. 861 to 865        [Non-Patent Document 2] PROCESS TECHNOLOGY FOR SILICON CARBIDE DEVICES pp. 51 to 67, published by INSPEC        